Analog Electronic Circuit Synthesis Using Simulated Annealing and Geometric Circuit Evolution

This article presents the SANN-GCE algorithm, a spice simulation driven meta-heuristic to design general discrete analog electronic circuits automatically, both circuit topology and component sizing. We introduce an encoding scheme called Geometric Circuit Evolution (GCE) that works associated with Simulated Annealing algorithm uses categorized degrees of freedom, allows distinct characteristics change different probabilities according its type during evolution. show through series seven active test SANN-GCE, compared benchmark, present median fitness 15.88 times better, standard deviation 6.72 lower between runs. The runtime found was 14.17 lower.